Memory is employed in a wide variety of integrated circuit applications and may be implemented, for example, as discrete memory or as embedded memory (e.g., with a processor and/or within a programmable logic device). One drawback of a conventional memory, for example, is that during the decoding of an address (e.g., for a dynamic wordline driver), multiple wordlines may be erroneously activated if the setup time is violated for the address decoding (e.g., address pre-decoding) and wordline enable signals. This error may occur, for example, due to the typical address pre-decoder having one output signal always high. Consequently, removing the old address signal may become as critical for timing purposes as providing the new address signal.
Typically, a delay path is employed to prevent the wordline-enable signal from activating too soon. However, in order to meet the setup time for the worst-case path (i.e., worst-case corner), the length of the delay is generally excessive for the typical path (e.g., to the other corners). The excessive delay generally results in lower performance for the memory, especially for the typical path (e.g., to the non-worst case corners). As a result, there is a need for improved memory techniques.